De-coupling capacitors have been employed for integrated circuits to reduce transient voltage and currents, and to manage loop currents and digital supply ripple that occur during integrated circuit chip operation. On-chip decoupling capacitors have been placed in the unused boundary areas of an integrated circuit, outside the active circuitry (outside the digital core) of the integrated circuit, in the spaces left empty by cell placement or frontier areas in or around the route. In the past, the amount of decoupling capacitors needed in the digital route to manage loop currents and digital supply ripple has defined the final digital cores size in spur-sensitive integrated circuits. This is mainly due to the low efficiency of the available decoupling cells and the need to have considerable in-route capacitance. This causes the maximum digital route utilization to be determined not by the routability of the core but by the amount of in-route cap needed.